We are currently looking for experienced Verification Engineers in our Flow Control Management
(FCM) division. Within IDT, the FCM division manages inter-chip data movement and buffering.
FCM devices are off-the-shelf products providing access and/or queuing for data streams between
subsystems and assist in additional functions such as policing, shaping, scheduling, and
directing data. 

 

Engineers will create verification plans at both the module and chip level for complex ICs. 
Will develop test benches using Vera/NTB, RVM.  Will develop efficient system/chip level test
and regression environment and scripts.  Will develop behavior models and BFM.  Will generate
test cases and run simulations to achieve code coverage and function coverage.

 

Position requirements:

* MSEE with 5-10 years of experience in a verification environment

* Proficiency in Vera/NTB

* Knowledge of scripting languages such as Verilog PLI/Direct C and System C

* Experience verifying high speed serial interfaces such as sRIO and PCIe is highly desirable