A qualified applicant for this position would be responsible for design, implementation, and
verification of network processor ASICs or components that lie within these ASICs. The position
includes working with a design team including other Digital Designers, Architects, Physical
Design Engineers, Test Engineers, and Product Engineers to develop the next generation digital
Systems on a Chip (SoC's) for applications in communication and networking. Responsibilities
will include logic design, implementation and verification of the design, and ensuring that the
design is suited for manufacturing test. This entails working closely with customers and/or
other peers on a regular basis. Participation from inital concept, through the creation,
testability, and prototype evaluation phase will be required. 

Experience in logic design, synthesis, DFT techniques, timing analysis, logic verification, and
layout of high-speed digital logic and circuit. Experience with ASIC EDA tools used in
synthesis, simulation, static timing analysis, test insertion and ATPG, and formal
verification. Knowledge of Verilog and C++ design languages. Excellent technical
troubleshooting and demonstrated problem-solving skills. Good written and verbal communication
skills. Willingness to work in highly visible and dynamic environment. Familiarity with design
concepts and architectures for complex packet processing functions is a plus. A minimum of a
BSEE and 5+ years of ASIC design experience